1. Field of the Invention
The present invention relates to a semiconductor memory device, and a redundancy method therefor.
2. Description of the Related Art
In recent years, attention has been focused on resistive memories as successive candidates for flash memories. The resistive memory devices include a resistive memory (ReRAM: Resistive RAM) in a narrow sense, which uses a transition metal oxide as a recording layer to nonvolatilely store the resistance value state thereof, and a phase change memory (PCRAM: Phase Change RAM), which uses a chalcogenide or the like as a recording layer to utilize the resistance value information on the crystalline state (conductor) and the amorphous state (insulator).
A variable resistor in the resistive memory has been known to have two types of operation modes. One is designed to switch the polarity of the applied voltage to set a high-resistance state and a low-resistance state. This is referred to as the bipolar type. The other is designed to control the voltage value and the voltage applying time without switching the polarity of the applied voltage. This is referred to as the unipolar type.
The unipolar type is preferable to realize a high-density memory cell array. This is because in the unipolar type a variable resistor and a rectifier such as a diode can be stacked at an intersection of a bit line and a word line to configure a cell array with cross-point type memory cells with the use of no transistor. Further, such cell arrays can be stacked and arrayed three-dimensionally to realize a high capacity without increasing the cell array area (see JP 2002-541613 A).
In a cross-point type memory cell, a diode may become defective, and then the memory cell may fall into a short-circuited state. In this case, even when a memory cell other than the defective cell in the same memory cell array is selected for normal read or normal write operation, a current flows in the defective cell, preventing the read or write operation from performed normally. When such a defective cell is detected, there may be a case when the whole memory cell array including the defective cell must be dealt as a subject of redundancy replacement. In such a case, it is possible to decrease the area of one memory cell array to improve the redundancy remedy efficiency. In this case, however, there is a problem that the area of the memory cell array becomes large.